ULA project is on track again, see Mods & Hacks for PDF doc, first version of reverse engineering of ULA5RA087 done! 😊 Check it out,...

Memory Mapper Design - PDF updated, wrong schematics for the MAPPER_D0D1_EA14EA15_LOGIC schematics See Mods & Hack section for download

1 Mars 2020 - PDF added with schematics and full investigation of the RTC logic and also non documented chips on-board investigated and...

This module will handle the L1-L7 out to the DRAM, we will also handle the extra A7 refresh line that in PHILIPS design is called ‘A7....

This part of the design that handles the EA14 and EA15 line out, and the D0-D3 (this are BIDIR lines) data lines with backward annotation...

How does the RW/WR logic to the mapper works? If all input signal to 8 input NAND are H output will be L otherwise combination it will be...

In my search for the mapper to the SVI738 i came a cross different mapper, schematics and information how people have solved this, but my...