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ULA reverse engineering - ULA5RA087
ULA project is on track again, see Mods & Hacks for PDF doc, first version of reverse engineering of ULA5RA087 done! 😊 Check it out,...

lkpalwa
Jul 31, 20201 min read
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Memory Mapper Design - Updated incorrect PDF
Memory Mapper Design - PDF updated, wrong schematics for the MAPPER_D0D1_EA14EA15_LOGIC schematics See Mods & Hack section for download

lkpalwa
Jul 26, 20201 min read
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Final Guide to RTC support published in Mods & Hacks
1 Mars 2020 - PDF added with schematics and full investigation of the RTC logic and also non documented chips on-board investigated and...

lkpalwa
Mar 4, 20201 min read
34 views
6 comments


MAPPER_L1L7_LOGIC
This module will handle the L1-L7 out to the DRAM, we will also handle the extra A7 refresh line that in PHILIPS design is called ‘A7....

lkpalwa
Feb 27, 20202 min read
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MAPPER_D0D1_EA14EA15_LOGIC
This part of the design that handles the EA14 and EA15 line out, and the D0-D3 (this are BIDIR lines) data lines with backward annotation...

lkpalwa
Feb 25, 20202 min read
4 views
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MAPPER_RW_RW_LOGIC
How does the RW/WR logic to the mapper works? If all input signal to 8 input NAND are H output will be L otherwise combination it will be...

lkpalwa
Feb 24, 20201 min read
8 views
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First Embryo of a Generic Memory mapper, limited to 256KB
In my search for the mapper to the SVI738 i came a cross different mapper, schematics and information how people have solved this, but my...

lkpalwa
Feb 23, 20202 min read
19 views
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