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This module will handle the L1-L7 out to the DRAM, we will also handle the extra A7 refresh line that in PHILIPS design is called ‘A7....


This part of the design that handles the EA14 and EA15 line out, and the D0-D3 (this are BIDIR lines) data lines with backward annotation...


How does the RW/WR logic to the mapper works? If all input signal to 8 input NAND are H output will be L otherwise combination it will be...

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