This module will handle the L1-L7 out to the DRAM, we will also handle the extra A7 refresh line that in PHILIPS design is called ‘A7. (do not get confused 'A7 is not the A7)
Input ports are ADR0 to ADR7, ADR8 to ADR13 plus EA14 and EA15 output from the previous module MAPPER_D0D1_EA14EA15_LOGIC. Also the /RFSH, /MREQ, MPX and /RESET is used in the design. (in the schematic picture the are prefix with M or Mi)
The MPX port (in some design called MUX) is the signal that toggle the two multiplexer chips LS157 when L it transfers ADR0 to ADR6 to the L0-L6 and when H it uses ADR8-ADR13 plus EA14 to the L0-L6 instead. (L7 with the ADR7 or EA15 is handle by the LS513 chip)
So if we simplify the logic the first LS157 handles lines L0 to L3 lines, and second L157 handles L4 to L6, the LS153 handle L7 where output is ‘A7, ADR7, ADR15 and L32+2xLS74 chips handle the additional ‘A7 refresh signal 😊
In MSX DATA PACK schematics for the memory logic they call this ROW\COL where ADR0-7 is ROW and ADR8-ADR15 is COL, this is how the Z80 CPU will be available to read or write to a specific memory cell when the D0-D7 bus contains read or write data from/to the DRAM.
Because the Z80 internal memory refresh (/RFSH) operation (increment lower 7 bits) only handles ADR0 to ADR6, when need to add an external logic that handles the ADR7 refresh.
In the design we used the ADR6 to create an additional refresh cycle for the ADR7 using the MiRFSH (/RFSH signal) and MiMREQ (/MREQ) and this is handled by the LS32 chip and the two LS74 chips only difference is that we added the MiRESET signal (/RESET) so when CPU reset its also do the ‘A7 reset. 😊
In the original PHILIPS schematic they use 4 NAND gates to handle ‘A7 and ADR7 lines, this is too complex to follow so I replace the logic using a LS153 chip (an one-bit wide 4 to 1 multiplexer) instead as design in the MSX DATA PACK (same logic vs simple logic 😊) and EXPERT2/3 schematics. when 'A7, ADR15 and ADR7 is passed to L7 depends on the MPX and MiRFSH (/RFSH) signal.