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MAPPER_D0D1_EA14EA15_LOGIC

This part of the design that handles the EA14 and EA15 line out, and the D0-D3

(this are BIDIR lines) data lines with backward annotation support.


Input lines to this module are /MiMAPRD and /MiMAPWR (see previous module) plus the MADR0, MADR1, MADR14 and MADR15. D0-D3 are also used as both input and output depending of state.


Start by looking at the LS157 chip, which is multiplexer and controlled by the /MAPiRD that goes into the port MAB. When MAB is L the MADR0 an MADRA1 are sent out to Y3 and Y4 and if H the MADR14 and MADR15 are sent out to Y3 and Y4 instead.


Now if we look into the part with LS125 chips, this are 3 state buffer, and the logic is very simple if EN are L then A=Y, and if EN are H the Y=Hi-Z. (Hi-Z is to effectively remove the output logic)


EN is handle by the / MiMAPRD line and to make a long story short if that is L then the output from LS670 chip is transfer to the D0-D3 lines, and if H its blocked.


Now to the more complex part, LS670 chip is 4 Word x 4 Bit register file logic and use following inputs D0-D3 as input to port D1-D4.


The D0 is buffered by the LS125 (always passed because EN is L)


GWN is the Write Enable port and is handled by the /MiMAPWR and the WA and WB are mapped to MADR0 and MADR1. WA and WB are Write Address Inputs.

GWN is L then it enable and disable when H (depending of the state of /MiMAPWR)


GRN is the Read Enable port is always L (mapped to GND) and the Read Address Inputs are handle by the RA and RB ports that are connected to MADR0-MADR1 (/MiMAPRD is L) or MADR14-MADR15 (/MiMAPRD is H).


The EA14 and EA15 output are mapped to Q1 and Q2, and always the WnB1 and WnB2 depending of RA and RB address that the LS157 passed through. (if /MiMAPRD is L or H)


Q1-Q4 is mapped to D0-D3 as output if /MiMAPRD is L (passed through the LS125 logic)


See table and Schematics to try to understand logic (its not easy - I think I got it right 😊)






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