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First Embryo of a Generic Memory mapper, limited to 256KB

In my search for the mapper to the SVI738 i came a cross different mapper, schematics and information how people have solved this, but my idea is to create a internal mapper and replace on-board 64KB with 256KB to have a full MSX2/MSX2+ after upgrade, issues I found was that the ULA that handle the SLT3-x is not correct, so that is part of the ULA project.


This mapper is very simple and can easy be implemented to other MSX computer.

So after doing some reverse engineering and looking at the internal memory mappers for the Philips NMS 8250, Yamaha YIS503, Expert2/3 schematics it landed into this design.

I also looked into the MSX Data Pack documentation, but the design there has no back annotation so it will not work in most European MSX-2(+) machines.


So to keep simple I divided the schematics into 3 blocks, and to keep it difficult 😊 I try to solve it using VHDL and CPLD chips, instead of traditional TTL LS chips, this way it will just be a EPM7064 and 2x44256 DRAM. But of course the design can be used implementing standard TTL LS chips. (bigger PCB board and more components is the backside)


So back to the design 😊 that is based on three build blocks, MAPPER_RW_WR_LOGIC,

MAPPER _D0D3_EA14EA15_LOGIC and MAPPER_L0L7_LOGIC.


MAPPER_RW_WR_LOGIC is handling the READ/WRITE logic for the mapper.

MAPPER _D0D3_EA14EA15_LOGIC handles the D0-D3 lines with backward annotation + the EA14/EA15 address out the MAPPER_L0L7_LOGIC.

MAPPER_L0L7_LOGIC handles the address lines L0-L7 that are connected to the DRAM address lines.

NO additional /RAS, /CAS or MPX signal needed those are supply ULA, and by using 2 chips no additional split of /CAS is needed.


#MSX #MAPPER #DESIGN

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