Updated: Feb 27

How does the RW/WR logic to the mapper works?

If all input signal to 8 input NAND are H output will be L otherwise combination it will be H, inputs are the lower address line A2 to A7 plus the /IORQ and /M1 signal from the CPU.

/IORQ signal indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. (Observe that the /IORQ is inverted before going into port a)

/M1 and /IORQ are both active, then that indicates an interrupt acknowledge cycle (an interrupt response vector can be placed on the data bus)

Now that output signal is the used together with the /RD and /WR using the OR gate to create the /MAPRD and /MAPWR signal.

/MAPRD and /MAPWR signal will only be L when /RD or /WR are L and the output from 8NAND is also L else it will be H. (this handle by LS32 NOR logic)

/RD Indicates that data is ready to be read from a memory or I/O device to the CPU.

/WR indicates that data is going to be written from the CPU data bus to a memory or I/O device.


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